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| fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos mb90800 series mb90803/f804/v800 n n n n description the mb90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed real- time processing required for industrial and office automation equipment and process control, etc. the lcd controller of 48 segment four common is built into. instruction set has taken over the same at architecture as in the f 2 mc*-8l and f 2 mc 16l, and is further enhanced to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and enrichment of bit processing. in addition, long word processing is now available by introducing a 32-bit accumulator. * : f 2 mc, an abbreviation for fujitsu flexible microcontroller, is a registered trademark of fujitsu ltd. n n n n features clock ? built-in pll clock frequency multiplication circuit ? operating clock (pll clock) can be selected from divided-by-2 of oscillation or 1 to 4 times the oscillation (at oscillation of 6.25 mhz, 6.25 mhz to 25 mhz). ? minimum instruction execution time of 40.0 ns (at oscillation of 6.25 mhz, four times the pll clock, operation at vcc = 3.3 v) the maximum memory space:16 mb ? 24-bit internal addressing ? bank addressing (continued) n n n n pac k ag e 100 - pin plastic qfp (fpt-100p-m06) r
mb90800 series 2 (continued) optimized instruction set for controller applications ? wide choice of data types (bit, byte, word, and long word) ? wide choice of addressing modes (23 types) ? high code efficiency ? enhanced high-precision computing with 32-bit accumulator ? enhanced multiply/divide instructions with sign and the reti instruction instruction system compatible with high-level language (c language) and multitask ? employing system stack pointer ? instruction set has symmetry and barrel shift instructions program patch function (2 address pointer) 4-byte instruction queue interrupt function ? the priority level can be set to programmable. ? interrupt function with 32 factors data transfer function ? expanded intelligent i/o service function (ei 2 os): maximum of 16 channels] low power consumption mode ? sleep mode (a mode that helts cpu operating clock) ? time-base timer mode (a mode that operates oscillation clock and time-base timer) ? watch timer mode (mode in which only the subclock and watch timers operate) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu blocking operation mode (operating cpu at each set cycle) package ? lqfp-120p (fpt-100p-m06:0.65 mm pin pitch) process : cmos technology mb90800 series 3 n n n n built-in peripheral function (resource) i/o port : 68 or less (sub - clocking 70 unused) time-base timer : 1channel watchdog timer : 1 channel watch timer : 1channel lcd controller ? 48seg 4com 8/10-bit a/d converter : 12 channels ? 8-bit resolution or 10-bit resolution can be set. 16-bit reload timer : 3 channels multi-functional timer ? 16-bit free run timer : 1 channel ? 16-bit output compare : 2 channels an interrupt request can be output when the count value of the 16-bit free-run timer and the setting value in the compare register match. ? input capture : 2 channels upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit free- run timer is loaded into the input capture data register and an interrupt request can be output. ? 16-bit ppg timer : 2 channels ? 16-bit reload timer : 3 channels uart : 2 channels extended i/o serial interface : 2 channels dtp/external interrupt circuit : 4 channels ? activate the extended intelligent i/o service by external interrupt input ? interrupt output by external interrupt input timer clock output circuit delay interrupt output module ? output an interrupt request for task switching i 2 c interface : 1 channel mb90800 series 4 n product lineup 1. mb90800 series part number mb90v800 MB90F804-101/201 mb90803/s type for evaluation flash memory built-in type mask rom built-in type system clock on-chip pll clock multiplication method( 1, 2, 3, 4, 1/2 when pll stops) minimum instruction execution time of 40.0 ns (at oscillation of 6.25 mhz, four times the pll clock) rom capacity no 256 kbytes 128 kbytes ram capacity 28 kbytes 16 kbytes 4 kbytes cpu functions number of basic instructions : 351 minimum instruction execution time : 40.0 ns/6.25 mhz oscillator (when four times is used : machine clock 25 mhz, power supply voltage : 3.3 v 0.3 v) addressing type : 23 types program patch function : 2 address pointers the maximum memory space : 16mb ports i/o port (cmos) 68 ports (shared with resources), (70 ports when the subclock is not used) lcd controller/driver segment driver that can drive the lcd panel (liquid crystal display) directly, and common driver 48 seg 4 com 16-bit input/ output timer 16-bit free-run timer 1 channel overflow interrupt output compare (ocu) 2 channels pin input factor: matching of the compare register input capture (icu) 2 channels rewriting a register value upon a pin input (rising edge, falling edge, or both edges) 16-bit reload timer 16-bit reload timer operation (toggle output, single shot output selectable) the event count function is optional. the event count function is optional. three channels are built in. 16-bit ppg timer output pin 2 ports operating clock frequency : fcp, fcp/22, fcp/24, fcp/26 two channels are built in. timer clock output circuit clock with a frequency of external input clock divided by 16/32/64/128 can be output externally. i 2 c bus i 2 c interface. 1 channel is built-in. 8/10-bit a/d converter 12 channels (input multiplex) the 8-bit resolution or 10-bit resolution can be set. conversion time : 5.9 m s (when machine clock 16.8 mhz works). uart full-duplex double buffer asynchronous/synchronous transmit (with start/stop bits) are supported. two channels are built in. extended i/o serial interface two channels are built in. interrupt delay interrupt four channel independence (a/d input and using combinedly) interrupt causes : ?l? ? ?h? edge/?h? ? ?l? edge/?l? level/?h? level selectable dtp/external interrupt 8 channels (the 8 channels include with the shared a/d input) interrupt causes ?l? ? ?h? edge/?h? ? ?l? edge/?l? level/?h? level selectable low power consumption mode sleep mode/timebase timer mode/watch mode/stop mode/cpu intermittent mode process cmos operating voltage 2.7 v to 3.6 v mb90800 series 5 n n n n pin assignment (top view) (fpt-100p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p24/seg32 p25/seg33 p26/seg34 p27/seg35 p30/seg36/so3 p31/seg37/sc3 p32/seg38/si3 p33/seg39/tmck p34/seg40/ic0 p35/seg41/ic1 p36/seg42/ocu0 p37seg43/ocu1 x0a/p90 x1a/p91 vcc vss p40/led0 p41/led1 p42/led2 p43/led3 p44/led4 p45/led5/tot0 p46/led6/tot1 p47/led7/tot2 p50/seg44/tin0 p51/seg45/tin1 p52/seg46/tin2/ppg0 p53/seg47/ppg1 p54/si0 p55/so0 p03/seg15 p02/seg14 p01/seg13 p00/seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 vss vcc seg1 seg0 p84/com3 p83/com2 com1 com0 v3 v2/p82 v1/p81 v0/p80 rst md0 md1 md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p56/so0 avcc p57/si1 p76 avss p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5/int0 p66/an6/int1 p67/an7/int2 vss p70/an8/int3 p71/an9/sc1 p72/an10/so1 p73/an11/si2 p74/sda/sc2 p75/scl/so2 p23/seg31 p22/seg30 p21/seg29 p20/seg28 p17/seg27 p16/seg26 p15/seg25 x0 x1 vss vcc p14/seg24 p13/seg23 p12/seg22 p11/seg21 p10/seg20 p07/seg19 p06/seg18 p05/seg17 p04/seg16 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mb90800 series 6 n n n n pin description * : for the circuit type, see section ? n i/o circuit type?. (continued) pin no. pin name circuit type* status/function at reset description qfp 92, 93 x0, x1 a oscillation status it is a terminal which connects the oscillator. when connecting an external clock, leave the x1 pin side unconnected. 13, 14 x0a, x1a b oscillation status it is 32 khz oscillation pin. (dual-line model) p90, p91 g port input (high-z) general purpose input/output port. (single-line model) 51 md2 m mode pins input pin for selecting operation mode. connect directly to vss. 52, 53 md1, md0 l mode pins input pin for selecting operation mode. connect directly to vcc. 54 rst k reset input external reset input pin. 63, 64, 67 to 72, 73 to 76 seg0 to seg11 d lcd seg output a segment output terminal of the lcd controller/ driver. 77 to 84 seg12 to seg19 e port input (high-z) a segment output terminal of the lcd controller/ driver. p00 to p07 general purpose input/output port. 85 to 89, 94 to 96 seg20 to seg27 e a segment output terminal of the lcd controller/ driver. p10 to p17 general purpose input/output port. 97 to 100, 1 to 4 seg28 to seg35 e a segment output terminal of the lcd controller/ driver. p20 to p27 general purpose input/output port. 5 seg36 e a segment output terminal of the lcd controller/ driver. p30 general purpose input/output port. so3 serial data output pin of serial i/o channel 3. valid when serial data output of serial i/o channel 3 is enabled. 6 seg37 e a segment output terminal of the lcd controller/ driver. p31 general purpose input/output port. sc3 serial clock i/o pin of serial i/o channel 3. valid when serial clock output of serial i/o channel 3 is enabled. mb90800 series 7 * : for the circuit type, see section ? n i/o circuit type?. (continued) pin no. pin name circuit type* status/function at reset description qfp 7 seg38 e port input (high-z) a segment output terminal of the lcd controller/ driver. p32 general purpose input/output port. si3 serial data input pin of serial i/o channel 3. this pin may be used at any time during serial i/o channel 3 in input mode, so do not use it as other pin function. 8 seg39 e a segment output terminal of the lcd controller/ driver. p33 general purpose input/output port. tmck timer clock output pin. it is effective when permitting the power output. 9, 10 seg40, seg41 e a segment output terminal of the lcd controller/ driver. p34, p35 general purpose input/output port. ic0, ic1 external trigger input pin of input capture channel 0/ channel 1. 11, 12 seg42, seg43 e a segment output terminal of the lcd controller/ driver. p36, p37 general purpose input/output port. ocu0, ocu1 output terminal for the output compares. 17 to 21 led0 to led4 f it is a output terminal for led (i ol = 15 ma). p40 to p44 general purpose input/output port. 22 to 24 led5 to led7 f it is a output terminal for led (i ol = 15 ma). p45 to p47 general purpose input/output port. tot0 to tot2 external event output pin of reload timer channel 0 to chanel 2. it is effective when permitting the external event output. 25, 26 seg44 to seg45 e a segment output terminal of the lcd controller/ driver. p50, p51 general purpose input/output port. tin0, tin1 external clock input pin of reload timer channel 0, channel 1. it is effective when permitting the external clock input. mb90800 series 8 * : for the circuit type, see section ? n i/o circuit type?. (continued) pin no. pin name circuit type* status/function at reset description qfp 27 seg46 e port input (high-z) a segment output terminal of the lcd controller/ driver. p52 general purpose input/output port. tin2 external clock input pin of reload timer channel 2. it is effective when permitting the external clock input. ppg0 ppg timer (ch0) output pin. 28 seg47 e a segment output terminal of the lcd controller/ driver. p53 general purpose input/output port. ppg1 ppg (ch1) timer output pin. 29 sio g serial data input pin of uart channel 0. this pin may be used at any time during uart channel 0 in receiving mode, so do not use it as other pin function. p54 general purpose input/output port. 30 sc0 g serial clock input/output pin of uart channel 0. it is effective when permitting the serial clock output of uart channel 0. p55 general purpose input/output port. 31 so0 g serial data output pin of uart channel 0. it is effective when permitting the serial clock output of uart channel 0. p56 general purpose input/output port. 33 si1 g serial data input pin of uart channel 1. this pin may be used at any time during uart channel 1 in receiving mode, so do not use it as other pin function. p57 general purpose input/output port. 34 p76 g general purpose input/output port. 36 to 40 an0 to an4 i analog input pin channel 0 to channel 4 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p60 to p64 general purpose input/output port. mb90800 series 9 * : for the circuit type, see section ? n i/o circuit type?. (continued) pin no. pin name circuit type* status/function at reset description qfp 41 to 43 an5 to an7 i analog input (high-z) analog input pin channel 5 to channel 7 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p65 to p67 general purpose input/output port. int0 to int2 functions as an external interrupt ch0 to ch2 input pin. 45 an8 i analog input pin channel 8 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p70 general purpose input/output port. int3 functions as an external interrupt ch3 input pin. 46 an9 i port input (high-z) analog input pin channel 9 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p71 general purpose input/output port. sc1 serial clock input/output pin of uart channel 1. it is effective when permitting the serial clock output of uart channel 1. 47 an10 i analog input pin channel 10 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p72 general purpose input/output port. so1 serial data output pin of serial i/o channel 1. valid when serial data output of serial i/o channel 1 is enabled. 48 an11 i analog input pin channel 11 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p73 general purpose input/output port. si2 serial data input pin of serial i/o channel 2. this pin may be used at any time during serial i/o channel 2 in input mode, so do not use it as other pin function. mb90800 series 10 (continued) * : for the circuit type, see section ? n i/o circuit type?. pin no. pin name circuit type* status/function at reset description qfp 49 sda h port input (high-z) data input/output pin of i 2 c interface. this function is enabled when the operation of the i 2 c interface is permitted. while the i 2 c interface is running, the port must be set for input use. p74 general purpose input/output port. (n-ch open drain) sc2 serial clock input pin of serial i/o channel 2. valid when serial clock output of serial i/o channel 2 is enabled. 50 scl h clock input/output pin of i 2 c interface. this function is enabled when the operation of the i 2 c interface is permitted. while the i 2 c interface is running, the port must be set for input use. p75 general purpose input/output port. (n-ch open drain) so2 serial data output pin of serial i/o channel 2. valid when serial data output of serial i/o channel 2 is enabled. 55 to 57 v0 to v2 j lcd drive power supply input lcd controller/driver. reference power terminals of lcd controller/driver. p80 to p82 general purpose input/output port. 59, 60 com0, com1 d lcd com output a common output terminal of the lcd controller/ driver. 61, 62 p83, p84 e port input (hi-z) general purpose input/output port. com2, com3 a common output terminal of the lcd controller/ driver. 32 avcc c power supply a/d converter exclusive power supply input pin. 35 avss c a/d converter-exclusive gnd power supply pin. 58 v3 j lcd controller/driver reference power terminals of lcd controller/driver. 15, 65, 90 vcc ? these are power supply input pins. 16, 44, 66, 91 vss ? gnd power supply pin. mb90800 series 11 n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistance : 1 m w approx. b ? low-rate oscillation feedback resistor, approx.10 m w c ? analog power supply input protection circuit d ? lcdc output e ? cmos output ? lcdc output ? hysteresis input (with input interception function at standby) x1 x0 pch nch clock input standby control signal x1a x0a pch nch clock input standby control signal pch avp nch pch nch lcdc output pch nch lcdc output input signal standby control signal mb90800 series 12 (continued) type circuit remarks f ? cmos output (heavy-current i ol =15 ma for led drive) ? hysteresis input (with input interception function at standby) g ? cmos output ? cmos hysteresis input (with input interception function at standby) mb90800 series 13 (continued) type circuit remarks j ? cmos output ? cmos hysteresis input (with input interception function at standby) ? lcd drive power supply input k ? cmos hysteresis input with pull-up resistor. l ? cmos hysteresis input m ? cmos hysteresis input with pull-down resistor pch nch input signal standby control signal lcd drive power supply reset input reset input input mb90800 series 14 n handling devices 1. preventing latchup, turning on power supply latchup may occur on cmosics under the following conditions: if a voltage higher than v cc or lower than v ss is applied to input and output pins, a voltage higher than the rated voltage is applied between v cc and v ss . if the av cc power supply is turned on before the v cc voltage. ensure that you apply a voltage to the analog power supply at the same time as v cc or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as v cc and the digital power supply). when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using cmosics, take great care to prevent the occurrence of latchup. 2. treatment of unused pins leaving unused input pins open could cause malfunctions. they should be connected to pull-up or pull-down registor. if the a/d converter is not used, connect the pins under the following conditions: avcc = vcc and avss = vss. 3. about the attention when the external clock is used ~ using external clock 4. treatment of power supply pins (v cc /v ss ) to prevent malfunctions of strobe signals due to the rise in the ground level, lower the level of unnecessary electro-magnetic emission, and prevent latchup, and conform to the total current rating in designing devices if multiple v cc or v ss pins exist. pay attention to connect a power supply to v cc and v ss of mb90800 series device in a lowest-possible impedance. in addition, near pins of mb90800 series device, connecting a bypass capacitor is recommended at 0.1 m f across v cc and v ss . 5. crystal oscillators circuit noise near the x0/x1 and x0a/x1a pin may cause the device to malfunction. design a print circuit so that x0/ x1 and x0a/x1a, a crystal oscillator (or a ceramic oscillator) , and bypass capacitor to the ground become as close as possible to each other. furthermore, avoid wires to crossing each other as much as possible. it is highly recommended that you should use a printed circuit board artwork because you can expect stable operations from it. 6. caution on operations during pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. performance of this operation, however, cannot be guaranteed. x0 x1 open mb90800 series 15 7. stabilization of supply power supply a sudden change in the supply voltage may cause the device to malfunction even within the v cc supply voltage operating range.therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak- to-peak values) at commercial frequencies (50 mhz/60 mhz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 8. note on using the two-subsystem product as one-subsystem product if you are using only one subsystem of the mb90800 series that come in one two-subsystem product, use it with x0a = vss and x1a = open. 9. write to flash ensure that you must write to flash at the operating voltage v cc = 3.13 v to 3.6 v. ensure that you must normal write to flash at the operating voltage v cc = 3.0 v to 3.6 v. mb90800 series 16 n n n n block diagram f 2 mc-16lx bus x0, x1 x0a * , x1a * rst v0/p80 v1/p81 v2/p82 v3 com0 com1 p83/com2 p84/com3 seg0-seg11 p00-p07/seg12-seg19 p10-p17/seg20-seg27 p20-p27/seg28-seg35 p30/seg36/so3 p31/seg37/sc3 p32/seg38/si3 p33/seg39/tmck p34/seg40/ic0 p35/seg41/ic1 p36/seg42/ocu0 p37/seg43/ocu1 p40/led0 p41/led1 p42/led2 p43/led3 p44/led4 p45/led5/tot0 p46/led6/tot1 p47/led7/tot2 p50/seg44/tin0 p51/seg45/tin1 p52/seg46/tin2/ppg0 p53/seg47/ppg1 p54/si0 p55/sc0 p56/so0 p57/si1 12 8 8 8 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5/int0 p66/an6/int1 p67/an7/int2 p70/an8/int3 p71/an9/sc1 p72/an10/so1 p73/an11/si2 p74/sda/sc2 p75/scl/so2 p76 p90 * p91 * ocu0/1 icu0/1 ppg0/1 uart0/1 ram (4/16/28 kb) rom/flash (128/256 kb) i 2 c clock control circuit cpu f 2 mc-16lx core lcd controller/ driver port 8 interrupt controller serial i/o 2/3 prescaler 2/3 free - run timer timer clock output reload timer 0/1/2 prescaler 0/1 10 bits ppg a/d converter external interrupt (4 ch) ? x0a/x1a and p90/p91 can be switched by mask option. specification of the evaluation device (mb90v800) built-in rom is not exist. the device has 28 kb built-in ram. port 0 port 1 port 2 port 4 port 3 port 5 port 6 port 7 port 9 mb90800 series 17 n n n n memory map memory map of mb90800 series notes : when the rom mirror function register has been set, the mirror image data at higher addresses ( "ff4000 h to ffffff h " ) of bank ff is visible from the higher addresses ( " 008000 h to 00ffff h " ) of bank 00. for setting of the rom mirror function, see ? n peripheral resource 17. rom mirror function selection module?. reference: ? the rom mirror function is for using the c compiler small model. ? the lower 16-bit addresses of bank ff are equivalent to those of bank 00. note that because the rom area of bank ff exceeds 32 k bytes, all data in the rom area cannot be shown in mirror image in bank 00. ? when the c compiler small model is used, the data table mirror image can be shown at " 008000 h to 00ffff h " by storing the data table at " ff8000 h to ffffff h . therefore, data tables in the rom area can be referenced without declaring the far addressing with the pointer. ffffff h 00ffff h 008000 h 007917 h 007900 h 000100 h 0000cf h 0000c0 h 0000bf h 000000 h * : rom is not built into v products. i must think rom decipherment region on the tool side. part number address # 1 address # 2 mb90803 0010ff h fe0000 h MB90F804 0040ff h fc0000 h mb90v800 0070ff h f80000 h * rom mirror function rom area address #2 address #2 rom mirror area extended io area 2 ram area register extended io area 1 io area mb90800 series 18 n f 2 mc - 16l cpuprogramming model ? dedicated registers ? general purpose registers ? processor status ah al dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16 bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70 mb90800 series 19 n n n n i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 - xxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 - - - xxxxx b 000009 h pdr9 port 9 data register r/w port 9 - - - - - - xx b 00000a h to 00000f h prohibited 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 - 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 - - - 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 - - - - - - 0 0 b 00001a h to 00001d h prohibited 00001e h ader0 analog input enable 0 r/w port 6, a/d 1 1 1 1 1 1 1 1 b 00001f h ader1 analog input enable 1 r/w port 7, a/d - - - - 1 1 1 1 b 000020 h smr0 mode register ch0 r/w uart0 0 0 0 0 0 - 0 0 b 000021 h scr0 control register ch0 r/w 0 0 0 0 0 1 0 0 b 000022 h s1dr0/ sodr0 input/output data register ch0 r/w xxxxxxxx b 000023 h ssr0 status register ch0 r/w 0 0 0 0 10 0 0 b 000024 h prohibited. 000025 h cdcr0 communication prescaler control register ch0 r/w prescaler 0 0 0 - - 0 0 0 0 b 000026 h to 000027 h prohibited mb90800 series 20 (continued) address register abbreviation register read/ write resource name initial value 000028 h smr1 mode register ch1 r/w uart1 0 0 0 0 0 - 0 0 b 000029 h scr1 control register ch1 r/w 0 0 0 0 0 1 0 0 b 00002a h sidr1/ sodr1 input/output data register ch1 r/w xxxxxxxx b 00002b h ssr1 status register ch1 r/w 0 0 0 0 1 0 0 0 b 00002c h prohibited 00002d h cdcr1 communication prescaler control reg- ister ch1 r/w prescaler 1 0 0 - - 0 0 0 0 b 00002e h prohibited 00002f h 000030 h enir external interrupt enable r/w external interrupt - - - - 0 0 0 0 b 000031 h eirr external interrupt request r/w xxxxxxxx b 000032 h elvr external interrupt level (lower) r/w 0 0 0 0 0 0 0 0 b 000033 h prohibited 000034 h adcs0 a/d control status register (lower) r/w a/d converter 0 0 - - - - - - b 000035 h adcs1 a/d control status register (upper) r/w 0 0 0 0 0 0 0 0 b 000036 h adcr0 a/d data register (lower) r xxxxxxxx b 000037 h adcr1 a/d data register (upper) r/w 0 0 1 0 1 xxx b 000038 h prohibited 000039 h admr a/d conversion channel set register r/w a/d converter 0 0 0 0 0 0 0 0 b 00003a h cpclr compare clear register r/w 16-bit free-run timer xxxxxxxx b 00003b h xxxxxxxx b 00003c h tcdt timer data register r/w 0 0 0 0 0 0 0 0 b 00003d h 0 0 0 0 0 0 0 0 b 00003e h tccsl timer control status register (lower) r/w 0 0 0 0 0 0 0 0 b 00003f h tccsh timer control status register (upper) r/w 0 - - 0 0 0 0 0 b 000040 h to 000043 h prohibited 000044 h ipcp0 input capture register 0 r input capture 0/1 xxxxxxxx b 000045 h xxxxxxxx b 000046 h ipcp1 input capture register 1 xxxxxxxx b 000047 h xxxxxxxx b 000048 h ics01 input capture control status 0/1 r/w 0 0 0 0 0 0 0 0 b 000049 h prohibited 00004a h occp0 output compare register 0 r/w output compare 0 xxxxxxxx b 00004b h xxxxxxxx b 00004c h occp1 output compare register 1 r/w output compare 1 xxxxxxxx b 00004d h xxxxxxxx b mb90800 series 21 (continued) address register abbreviation register read/ write resource name initial value 00004e h ocsl output compare control status (lower) r/w output compare 0/1 0 0 0 0 - - 0 0 b 00004f h ocsh output compare control status (upper) r/w - - - 0 0 0 0 0 b 000050 h tmcsr0l timer control status register 0 (lower) r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 000051 h tmcsr0h timer control status register 0 (upper) r/w - - - - 0 0 0 0 b 000052 h tmr0/ tmrlr0 timer register 0/reload register 0 r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmcsr1l timer control status register 1 (lower) r/w reload timer 1 0 0 0 0 0 0 0 0 b 000055 h tmcsr1h timer control status register 1 (upper) r/w - - - - 0 0 0 0 b 000056 h tmr1/ tmrlr1 timer register 1/reload register 1 r/w xxxxxxxx b 000057 h xxxxxxxx b 000058 h tmcsr2l timer control status register 2 (lower) r/w reload timer 2 0 0 0 0 0 0 0 0 b 000059 h tmcsr2h timer control status register 2 (upper) r/w - - - - 0 0 0 0 b 00005a h tmr2/ tmrlr2 timer register 2/reload register 2 r/w xxxxxxxx b 00005b h xxxxxxxx b 00005c h lcrl lcdc control register (lower) r/w lcd controller/ driver 0 0 0 1 0 0 0 0 b 00005d h lcrh lcdc control register (upper) r/w 0 0 0 0 0 0 0 0 b 00005e h lcrr lcdc range register r/w 0 0 0 0 0 0 0 0 b 00005f h prohibited 000060 h smcs0 serial mode control status register (ch2) r/w sio (extended serial i/o) - - - - 0 0 0 0 b 000061 h 0 0 0 0 0 0 1 0 b 000062 h sdr0 serial data register (ch2) r/w xxxxxxxx b 000063 h sdcr0 control register of clock dividing frequency (ch2) r/w communication prescaler (sio) 0 - - - 0 0 0 0 b 000064 h smcs1 serial mode control status register (ch3) r/w sio (extended serial i/o) - - - - 0 0 0 0 b 000065 h 0 0 0 0 0 0 1 0 b 000066 h sdr1 serial data register (ch3) r/w xxxxxxxx b 000067 h sdcr1 control register of clock dividing frequency (ch3) r/w communication prescaler (sio) 0 - - - 0 0 0 0 b 000068 h prohibited 000069 h 00006a h ibsr i 2 c bus status register r i 2 c 0 0 0 0 0 0 0 0 b 00006b h ibcr i 2 c bus control register r/w 0 0 0 0 0 0 0 0 b 00006c h iccr i 2 c bus clock selection register r/w - - 0xxxxx b 00006d h iadr i 2 c bus address register r/w - xxxxxxx b 00006e h idar i 2 c bus data register r/w xxxxxxxx b 00006f h romm rom mirror w rom mirror xxxxxxx1 b mb90800 series 22 (continued) address register abbreviation register read/ write resource name initial value 000070 h pdcrl0 ppg0 down counter register r 16 bit ppg0 1 1 1 1 1 1 1 1 b 000071 h pdcrh0 1 1 1 1 1 1 1 1 b 000072 h pcsrl0 ppg0 cycle set register w xxxxxxxx b 000073 h pcsrh0 xxxxxxxx b 000074 h pdutl0 ppg0 duty setting register w xxxxxxxx b 000075 h pduth0 xxxxxxxx b 000076 h pcntl0 ppg0 control status register r/w - - 0 0 0 0 0 0 b 000077 h pcnth0 0 0 0 0 0 0 0 - b 000078 h pdcrl1 ppg1 down counter register r 16 bit ppg1 1 1 1 1 1 1 1 1 b 000079 h pdcrh1 1 1 1 1 1 1 1 1 b 00007a h pcsrl1 ppg1 cycle set register w xxxxxxxx b 00007b h pcsrh1 xxxxxxxx b 00007c h pdutl1 ppg1 duty setting register w xxxxxxxx b 00007d h pduth1 xxxxxxxx b 00007e h pcntl1 ppg1 control status register r/w - - 0 0 0 0 0 0 b 00007f h pcnth1 0 0 0 0 0 0 0 - b 000080 h to 000095 h (reserved) 000096 h prohibited 000097 h (reserved) 000098 h to 00009d h prohibited 00009e h pacsr rom correction control register r/w rom correction 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt/release r/w delayed interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selector r/w 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h prohibited 0000a8 h wdtc watchdog control r/w watchdog timer xxxxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h wtc watch timer control register r/w watch timer (sub clock) 1 x0 1 1 0 0 0 b 0000ab h to 0000ad h prohibited mb90800 series 23 (continued) ? read/write ? initial values address register abbreviation register read/ write resource name initial value 0000ae h fmcs flash control register r/w flash i/f 0 0 0 x 0 0 0 0 b 0000af h tmcs timer clock output control register r/w timer clock devide xxxxx 0 0 0 b 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 001ff0 h padr0 program address detection register 0 r/w address matching detection function xxxxxxxx b 001ff1 h r/w xxxxxxxx b 001ff2 h r/w xxxxxxxx b 001ff3 h padr1 program address detection register 1 r/w xxxxxxxx b 001ff4 h r/w xxxxxxxx b 001ff5 h r/w xxxxxxxx b 007900 h to 007917 h vram lcd display ram r/w lcd controller/ driver xxxxxxxx b r/w readable and writable r read only w write only 0 initial value is ?0?. 1 initial value is ?1?. x initial value is indeterminate. mb90800 series 24 n interrupt sources, interrupt vectors and interrupt control registers : available : unavailable : available el 2 os function is provided. : available when a cause of interrupt sharing a same icr is not used. * : when interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector number has the priority. ? when there are two interrupt causes in the same interrupt control register (icr) and use of iios is enabled, iios is started upon detection of one of the interrupt causes. as interrupts other than the start cause are masked during iios start, masking one of the interrupt requests is recommended when using iios. ? for a resource that has two interrupt causes in the same interrupt control register (icr), the interrupt flag is cleared by an iios interrupt clear signal. interrupt source ei 2 os readiness interrupt vector interrupt control register priority number* address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? dtp/external interrupt ch0 #11 0b h ffffd0 h icr00 0000b0 h dtp/external interrupt ch1 #13 0d h ffffc8 h icr01 0000b1 h serial i/o ch2 #15 0f h ffffc0 h icr02 0000b2 h dtp/external interrupt ch2/3 #16 10 h ffffbc h serial i/o ch3 #17 11 h ffffb8 h icr03 0000b3 h 16-bit free-run timer #18 12 h ffffb4 h watch timer #19 13 h ffffb0 h icr04 0000b4 h 16-bit reload timer ch2 #21 15 h ffffa8 h icr05 0000b5 h 16-bit reload timer ch0 #23 17 h ffffa0 h icr06 0000b6 h 16-bit reload timer ch1 #24 18 h ffff9c h input capture ch0 #25 19 h ffff98 h icr07 0000b7 h input capture ch1 #26 1a h ffff94 h ppg timer ch0 counter-borrow #27 1b h ffff90 h icr08 0000b8 h output compare match #29 1d h ffff88 h icr09 0000b9 h ppg timer ch1 counter-borrow #31 1f h ffff80 h icr10 0000ba h time-base timer #33 21 h ffff78 h icr11 0000bb h uart0 reception end #35 23 h ffff70 h icr12 0000bc h uart0 transmission end #36 24 h ffff6c h a/d converter conversion termination #37 25 h ffff68 h icr13 0000bd h i 2 c interface #38 26 h ffff64 h uart1 : reception #39 27 h ffff60 h icr14 0000be h uart1 : transmission #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delayed interrupt output module #42 2a h ffff54 h low mb90800 series 25 n n n n peripheral resources 1. i/o port the i/o ports function to output data from the cpu to i/o pins via their port data register (pdr) and send signals input to i/o pins to the cpu. in addition, the port can randomly set the direction of the input/output of the i/o pin in bit by the port direction register (ddr). the mb90800 series has 68 (70 ports when the subclock is not used) input/output pins. port0 to port8 (port0 to port9 when the subclock is not used) are input/output port. (1) port data register when reading : read the corresponding pin level. when writing : write into the latch for the input/output. output mode when reading : read the value of the data register latch. when writing : write into the corresponding pin. pdr0 initial value access address : 000000 h indeterminate r/w* pdr1 address : 000001 h indeterminate r/w* pdr2 address : 000002 h indeterminate r/w* pdr3 address : 000003 h indeterminate r/w* pdr4 address : 000004 h indeterminate r/w* pdr5 address : 000005 h indeterminate r/w* pdr6 address : 000006 h indeterminate r/w* pdr7 address : 000007 h indeterminate r/w* pdr8 address : 000008 h indeterminate r/w* pdr9 address : 000009 h indeterminate r/w* 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 15 14 13 12 11 10 9 8 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 15 14 13 12 11 10 9 8 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 15 14 13 12 11 10 9 8 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p65 p64 p63 p62 p61 p60 p67 15 14 13 12 11 10 9 8 p76 p75 p74 p73 p72 p71 p70 ? 7654 321 0 p84 p83 p82 p81 p80 ? ? ? 15 14 13 12 11 10 9 8 p91 p90 ? ? ? ? ? ? mb90800 series 26 (2) port direction register ? when each terminal functions as a port, each correspondent pin are controlled to following; 0 : input mode 1 : output mode this bit becomes ?0? after a reset. note : when accessing this register by using the instruction of the read modify write system (instructions such as bit set) is mode, the bit targeted by an instruction becomes the defined value, while the content of the output register set with the other. therefore, be sure to write an expected value into pdr firstly, and then set ddr and finally change to the output when changing the input pin to the output pin is made. ddr0 initial value access address : 000010 h 00000000 b r/w ddr1 address : 000011 h 00000000 b r/w ddr2 address : 000012 h 00000000 b r/w ddr3 address : 000013 h 00000000 b r/w ddr4 address : 000014 h 00000000 b r/w ddr5 address : 000015 h 00000000 b r/w ddr6 address : 000016 h 00000000 b r/w ddr7 address : 000017 h - 0000000 b r/w ddr8 address : 000018 h - - - 00000 b r/w ddr9 address : 000019 h - - - - - - 00 b r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d 00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 15 14 13 12 11 10 9 8 d36 d37 d35 d34 d33 d32 d31 d30 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 15 14 13 12 11 10 9 8 d56 d57 d55 d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 15 14 13 12 11 10 9 8 d75 d74 d73 d72 d71 d70 d76 ? 7654 321 0 d84 d83 d82 d81 d80 ? ? ? 15 14 13 12 11 10 9 8 d91 d90 ? ? ? ? ? ? mb90800 series 27 (3) analog input enable register control each pin of port 6 as follows. 0 : port input/output mode. 1 : analog input mode.this bit becomes ?1? after a reset. ader0 initial value access address : 00001e h 11111111 b r/w ader1 address : 00001f h - - - - 1111 b r/w 7654 321 0 ade3 ade2 ade1 ade0 ade7 ade6 ade5 ade4 15 14 13 12 11 10 9 8 ade11 ade10 ade9 ade8 ???? mb90800 series 28 2. uart uart is a serial i/o port for asynchronous (start-stop synchronization) communication or clk synchronous communications. ? with full-duplex double buffer ? clock asynchronous (start-stop synchronization) , clk synchronous communications (no start-bit/stop-bit) can be used. ? supports multi-processor mode ? built-in dedicated baud rate generator asynchronous : 120192/60096/30048/15024/781.25 k/390.625 kbps clk synchronous : 25 m/12.5 m/6.25 m/3.125 m/1.5627 m/781.25 kbps ? variable baud rate can be set by an external clock. ? 7-bits data length (only asynchronous normal mode) /8-bits length ? master/slave type communication function (at multiprocessor mode) : the communication between one (mas- ter) to n (slave) can be operating. ? error detection functions(parity, framing, overrun) ? transmission signal format is nrz mb90800 series 29 (1) register list serial mode register (smr) serial control register(scr) serial input/output register (sidr/sodr) serial data register (ssr) communication prescaler control register (cdcr) address : 000020 h 000028 h initial value address : 000021 h 000029 h initial value address : 000022 h 00002a h initial value address : 000023 h 00002b h initial value address : 000025 h 00002d h initial value smr ? cdcr scr 15 0 sidr (r)/sodr (w) ssr 87 8 bit 8 bit (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 md0 (r/w) ( 0 ) md1 cs2 cs1 cs0 ? scke soe (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 p (r/w) ( 0 ) pen sbl cl a/d rec rxe txe (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ore ( r ) ( 0 ) pe fre rdrf tdre bds rie tie (r/w) ( 0 ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 urst (r/w) ( 0 ) md ?? div2 div1 div0 reserved mb90800 series 30 (2) block diagram md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rex txe pe ore fre rdrf tdre bds rie tie f 2 mc-16lx bus sidr sodr control signal 16-bit reload timer 0 pin clock selection circuit receive status decision circuit reception error occurrence signal for ei 2 os (to cpu) reception clock reception control circuit start bit detection circuit reception bit counter reception parity counter rx shifter reception control circuit transmission clock rx interrupt (to cpu) tx interrupt (to cpu) transmission control circuit transmission start circuit transmission bit counter transmission parity counter tx shifter start transmission smr register control signal scr register ssr register special-purpose baud-rate generator pin pin mb90800 series 31 3. i 2 c interface i 2 c interface is the serial input/output port that support inter ic bus and functions as the master/slave device on the i 2 c bus. mb90800 series have 1 channel of the built-in i 2 c interface. it has the features of i 2 c interface below. ? master/slave sending and receiving ? arbitration function ? clock synchronization function ? slave address and general call address detection function ? detecting transmitting direction function ? repeat generating and detecting function of the start conditions ? bus error detection function ? the forwarding rate can be supported to 100 kbps. (1) register list i 2 c status register (ibsr) i 2 c control register (ibcr) i 2 c clock control register (iccr) i 2 c data register(idar) i 2 c address register (iadr) initial value address :00006a h 00000000 b address :00006b h 00000000 b address :00006c h xx0xxxxx b address :00006e h xxxxxxxx b address :00006d h xxxxxxxx b 7654 321 0 rsc bb al lrb trx aas gca fbt r rrrrrrr 15 14 13 12 11 10 9 8 beie ber scc mss ack gcaa inte int r/w r/w r/w r/w r/w r/w r/w r/w 7654 321 0 ? ? en cs4 cs3 cs2 cs1 cs0 ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 d6 r/w d7 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w 7654 3210 a6 ? ? a5 a4 a3 a2 a1 a0 mb90800 series 32 (2) block diagram iccr 5 2 4 8 16 32 64 128 256 sync first byte 678 en iccr cs4 cs3 ibsr last bit irq idar iadr scl sda bb rsc lrb trx fbt al ibcr ber beie inte int ibcr scc mss ack gcaa ibsr aas gca cs2 cs1 cs0 internal data bus i 2 c enable clock divide 1 machine clock clock selector 1 clock divide 2 clock selector 2 generating shift clock change timing of shift clock edge bus busy repeat start transfer/ reception start stop condition detection arbitration lost detection interrupt request start master ack enable gc-ack enable start stop condition detection slave address compare slave global call error end mb90800 series 33 4. extended i/o serial interface the extended i/o serial interface is a serial i/o interface that can transfer data through the adoption of 8 bit 2 channel configured clock synchronization scheme. the extended i/o serial interface also has two alternatives in data transfer called lsb first and msb sirst. the serial i/o interface operates in two modes: (1) register list ? internal shift clock mode : transfer data in sync with the internal clock. ? external shift clock mode : transfers data in sync with the clock input through an external pin (sck) . in this mode, transfer operation performed by the cpu instruction is also available by operating the general-use port sharing an external pin (sck) . serial mode control status register(smcs) serial data register (sdr) communication prescaler control register (sdcr0, sdcr1) initial value address : 000060 h 000064 h 00000010 b address : 000061 h 000065 h ----0000 b address : 000062 h 000066 h xxxxxxxx address : 000063 h 000067 h 0---0000 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt r/w r/w r/w r/w r/w r r/w r/w 7654 321 0 ? ??? mode bds soe scoe r/w r/w r/w r/w ???? 7654 321 0 d6 d7 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w ??? r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ? r/w md ?? div2 div1 div0 reserved mb90800 series 34 (2) block diagram si2, si3 so2, so3 sc2, sc3 smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb fast) d0 to d7 (lsb fast) d7 to d0 sdr (serial data register) internal clock internal data bus transfer direction selection read write control circuit shift clock counter interrupt request internal data bus initial value mb90800 series 35 5. 8/10-bit a/d converter a/d converter converts an analog input voltage into digital value. the feature of a/d converter is shown as follows. ? conversion time : 3.1 m s minimum per 1 channel (78 machine cycle/at machine clock 25 mhz/including the sampling time) ? sampling time : 2.0 m s minimum per 1channel (50 machine cycle/at machine clock 25 mhz) ? uses rc-type successive approximation conversion method with a sample & hold circuit ? 8-bit resolution or 10-bit resolution can be select. ? 12 channel program-selectable analog inputs. single conversion mode : convert 1 specified channel scan conversion mode : continuous plural channels (maximum 12 channels can be programmed) are converted. continuous conversion mode : selected channel converted continuously. stop conversion time : perform conversion for one channel, then wait for the next activation trigger (synchronizes the conversion start timing) ?ei 2 os can be activated by outputting the interrupt request when the a/d conversion completes. ? if the a/d conversion is performed under the condition of the interrupt enable, the converting data will be protected. ? selectable conversion activation trigger : software, or reload timer (rising edge) (1) register list adcs1, adcs0 (control status register) adcr1, adcr0 (data register) adcs0 address : 000034 h ? initial value ? bit adcs1 bit address : 000035 h ? initial value ? bit adcr0 bit address : 000036 h ? initial value ? bit adcr1 bit address : 000037 h ? initial value ? bit 0 r/w ? ? ? ? ? ? ? ? ? ? ? ? 7654 3210 md0 0 r/w md1 ???? ?? 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 0 r/w 15 14 13 12 11 10 9 8 int 0 r/w busy inte paus sts1 sts0 strt reserved x r x r x r x r x r x r x r 7654 3210 d6 x r d7 d5 d4 d3 d2 d1 d0 0 w 1 w 0 w 1 w ? ? x r x r 15 14 13 12 11 10 9 8 st1 0 w s10 st0 ct1 ct0 ? d9 d8 mb90800 series 36 (2) block diagram f mp an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 adcr0, adcr1 adcs0, adcs1, av cc avr av ss admr input circuit d/a converter sequential compare register data register a/d control register 0 a/d control register 1 prescaler operation clock timer start-up decoder comparator sample & hold circuit 16 - bit reload timer data bus a/d channel set register mb90800 series 37 6. 16 bits ppg the ppg timer consists of the prescaler, one 16-bit down-counter, one 16-bit data register with a cycle setting buffer, a 16-bit compare register with a duty setting buffer, and the pin control unit. the ppg timer can output pulses synchronized to the software trigger. the period and duty of the output pulse can be changed freely by updating two 16-bit register values. ? pwm function the ppg timer can output pulses programmably by updating the values of the registers described above in synchronization to the trigger. can also be used as a d/a converter by an external circuit. ? single shot function by detecting an edge of the trigger input, a single pulse can be output. ? 16-bit down counter the counter operation clock comes from eight kinds optional. there are eight kinds of internal clocks. ( f , f 2, f 4, f 8, f 16, f 32, f 64, f 128) f : machine clock the counter is initialized to " ffff h " at a reset or counter borrow. ? interrupt request the ppg timer generates an interrupt request when : timer start-up/counter borrow occurs (cycle match) /duty match occurs/counter borrow occurs (cycle match) , or duty match occurs. mb90800 series 38 (1) register list pcnth (pcnth0/1 control status register) pcntl (pcntl0/1 control status register) pdcrh (pdcrh0/1 ppg down counter register) pdcrl (pdcrl0/1 ppg down counter register) pcsrh (pcsrh0/1 ppg cycle set register) pcsrl (pcsrh0/1 ppg cycle set register) pduth (pduth0/1 ppg duty set register) pdutl (pdutl0/1 ppg duty set register) 000077 h 00007f h read/write initial value 000076 h 00007e h read/write initial value 000071 h 000079 h read/write initial value 000070 h 000078 h read/write initial value 000073 h 00007b h read/write initial value 000072 h 00007a h read/write initial value 000075 h 00007d h read/write initial value 000074 h 00007c h read/write initial value ( r/w ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( r/w ) ( 0 ) ( r/w ) ( 0 ) ( r/w ) ( x ) 15 14 13 12 11 10 9 8 stgr (r/w) ( 0 ) cnte mdse rtrg csk2 csk1 csk0 pgms ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 ? ( ? ) ( ? ) ? iren irqf irs1 irs0 poen osel (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) 15 14 13 12 11 10 9 8 dc14 (r) ( 1 ) dc15 dc13 dc12 dc11 dc10 dc09 dc08 (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) (r) ( 1 ) 7654 3210 dc06 (r) ( 1 ) dc07 dc05 dc04 dc03 dc02 dc01 dc00 (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) 15 14 13 12 11 10 9 8 cs14 (w) ( x ) cs15 cs13 cs12 cs11 cs10 cs09 cs08 (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) 7654 3210 cs06 (w) ( x ) cs07 cs05 cs04 cs03 cs02 cs01 cs00 (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) 15 14 13 12 11 10 9 8 du14 (w) ( x ) du15 du13 du12 du11 du10 du09 du08 (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) (w) ( x ) 7654 3210 du06 (w) ( x ) du07 du05 du04 du03 du02 du01 du00 mb90800 series 39 (2) block diagram ~ 16-bit g ch0/1 block diagram 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 pcsr ck pdut cmp sq r prescaler pcnt 16-bit down counter load borrow start machine clock f enable soft trigger ppg mask ppg output reverse bit interrupt interrupt select mb90800 series 40 7. delay interrupt generator module the delayed interrupt generation module outputs an interrupt request for task swiching. when the delayed interrupt generation module is used, software is allowed to output and clear task switching interrupts for the mb90800 series cpu. (1) register list (2) block diagram delayed interrupt/release register(dirr) dirr initial value address : 00009f h - - - - - - - 0 b 15 14 13 12 11 10 9 8 ??????? r/w ? ? ????? r0 f 2 mc-16lx bus delay interruption factor generation/ release decoder factor latch mb90800 series 41 8. dtp/external interrupt dtp (data transfer peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal, and outputs the interrupt request. (1) register list (2) block diagram interrupt/dtp enable register (enir : enable interrupt request register) interrupt/dtp source register (eirr : external interrupt request register) request level setting register (elvr : external level register) enir initial value address : 000030 h - - - - 0000 b eirr initial value address : 000031 h - - - - xxxx b initial value address : 000032 h 00000000 b 7654 3210 ???? r/w r/w r/w r/w ? ??? en3 en2 en1 en0 15 14 13 12 11 10 9 8 ???? r/w r/w r/w r/w ? ??? er3 er2 er1 er0 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w la3 lb3 lb2 la2 lb1 la1 lb0 la0 4 4 4 8 4 f 2 mc-16lx bus interrupt/dtp enable register gate source f/f edge detection circuit request input interrupt/dtp source register request level setting register mb90800 series 42 9. 16-bit input/output timer the 16-bit i/o timer consists of one 16-bit free-run timer, two output compare and two input capture modules. this function enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and external clock frequencies to be measured. ~ register list ~ 16-bit free-run timer ~ 16-bit output compare ~ 16-bit input capture cpclr 15 0 00003b/3a h 00003d/3c h 00003f/3e h tcdt tccs compare clear register timer counter data register timer counter control status register occp0 ~ occp1 15 0 ocsl ocsh 00004a h /00004b h / 00004c h /00004d h 00004f h /00004e h compare register control status register ipcp0, ipcp1 15 0 ics01 000044 h /000045 h / 000046 h /000047 h 000048 h data register control status register mb90800 series 43 ~ block diagram tq tq ote0 ote1 ic0 ic1 bus 16-bit free-run timer output compare 0 output compare 1 control logic interrupt 16-bit timer compare register 0 clear compare register 1 capture register 0 capture register 1 to each block edge select edge select input capture 0 input capture 1 mb90800 series 44 (1) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up-down counter and control status register. counter value of 16-bit free-run timer is available as base timer for input capture and output compare. ? clock for the counter operation can be selected from eight types. ? the counter overflow interruption can be generated. ? setting the mode enables initialization of the counter through compare-match operation with the value of the compare clear register in the output compare. ~ register list compare clear register (cpclr) timer counter data register (tcdt) timer counter control/status register (tccs) initial value 00003b h xxxxxxxx b initial value 00003a h xxxxxxxx b initial value 00003d h 00000000 b initial value 00003c h 00000000 b initial value 00003f h 0--00000 b initial value 00003e h 00000000 b 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) cl14 cl15 cl13 cl12 cl11 cl10 cl09 cl08 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) cl06 cl07 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) t14 t15 t13 t12 t11 t10 t09 t08 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) t06 t07 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? ecke ? msi2 msi1 msi0 iclr icre 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ivfe ivf stop mode sclr clk2 clk1 clk0 mb90800 series 45 ~ block diagram ivf ivfe stop mode sclr clk1 clk0 iclr msi2 ~ msi0 icre clk2 f bus interrupt request 16-bit free-run timer count value output t15 to t00 divider clock interrupt request 16-bit compare clear register compare cir- mb90800 series 46 (2) output compare the output compare consists of 16-bit compare registers, compare output pin part and a control register. it can reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer value matches a value set in one of the 16-bit compare registers of this module. ? it has a total of six compare registers that can operate independently. in addition, the output can be set to be controlled by using two compare registers. ? an interrupt can be set by a comparing match. ~ register list compare register (occp0, occp1) control register (ocsh) control register (ocsl) initial value 00004b h 00004d h 00000000 b initial value 00004a h 00004c h 00000000 b initial value 00004f h ---00000 b initial value 00004e h 0000--00 b 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) op14 op15 op13 op12 op11 op10 op09 op08 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) op06 op07 op05 op04 op03 op02 op01 c00 15 14 13 12 11 10 9 8 ( ? )( ? )( ? ) (r/w) (r/w) (r/w) (r/w) (r/w) ? ?? cmod ote1 ote0 otd1 otd0 7654 321 0 (r/w) (r/w) (r/w) (r/w) ( ? )( ? ) (r/w) (r/w) iop0 iop1 ioe1 ioe0 ?? cst1 cst0 mb90800 series 47 ~ block diagram icp1 icp0 ice0 ice0 tq tq cmod ote1 ote0 bus 16-bit timer counter value (t15 to t00) compare control compare register 0 16-bit timer counter value (t15 to t00) compare control compare register 1 control logic each control blocks #29 #29 interrupt mb90800 series 48 (3) input capture this module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16- bit free-run timer in a register at the time of detection. it can also generate an interrupt when detecting an edge. the input capture consists of input capture and control registers. each input capture has its corresponding external input pin. ? the detection edge of an external input can be selected from among three types. rising edge/falling edge/ both edges. ? it can generate an interrupt when it detects the valid edge of the external input. ~ register list input capture data register (ipcp0, ipcp1) control status register (ics01) initial value 000045 h 000047 h xxxxxxxx b initial value 000044 h 000046 h xxxxxxxx b initial value 000048 h 00000000 b 15 14 13 12 11 10 9 8 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 7654 321 0 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00 mb90800 series 49 ~ block diagram ic0 eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 ic1 bus capture data register 0 16-bit timer counter value (t15 to t00) capture data register 1 edge detection edge detection interrupt #25 interrupt #25 mb90800 series 50 10. 16-bit reload timer the 16-bit reload timer provides two functions either one which can be selected, the internal clock the performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbitration. this timer defines an underflow as a transition of the count value from 0000 h to ffff h . therefore, when the equation (counted value = reload register setting value + 1) holds, an underflow occurs. either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. the interrupt can be generated at the counter underflow occurrence so as to corre- spond to the dtc. (1) register list tmcsrtimer control status register timer control status register (upper) (tmcsr) timer control status register (lower) (tmcsr) 16-bit timer register/16 - bit reload register tmr/tmrlr (upper) tmr/tmrlr (low) 000051 h 000055 h 000059 h read/write initial value 000050 h 000054 h 000058 h read/write initial value 000053 h 000057 h 00005b h read/write initial value 000052 h 000056 h 00005a h read/write initial value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? ( ? ) ( ? ) ??? csl1 csl0 mod2 mod1 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 oute (r/w) ( 0 ) mod0 outl reld inte uf cnte trg (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 d14 (r/w) ( x ) d15 d13 d12 d11 d10 d9 d8 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 mb90800 series 51 (2) block diagram tmrlr tmr en oute reld outl clk clk uf 3 3 2 internal data bus 16-bit reload register 16-bit timer register (down counter) count clock generation circuit machine clock f prescaler valid clock identification circuit gate input clear pin input control circuit external clock select function select signal timer control status register (tmcsr) clock selector reload signal wait signal output signal generation circuit output signal generation circuit pin reload control circuit re- verse operation control circuit mb90800 series 52 11. watch timer the watch timer is a 15-bit timer using the subclock. it can generate interval interrupts. the watch timer can also be used as the clock source of the watchdog timer by setting so. (1) register list (2) block diagram watch timer control register (wtc) 0000aa h initial value ( r ) ( x ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 sce (r/w) ( 1 ) wdcs wtie wtof wtr wtc2 wtc1 wtc0 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 10 2 13 2 14 2 15 sub clock watch counter interval selector interrupt generation circuit watch timer interrupt to watchdog timer watch timer control register (wtc) clear mb90800 series 53 12. watchdog timer the watchdog timer is a 2-bit counter operating with an output of the timebase timer or watch timer and resets the cpu when the counter is not cleared for a preset period of time. (1) register list (2) block diagram watchdog timer control register (wdtc) 0000a8 h initial value ( ? ) ( x ) ( r ) ( x ) ( r ) ( x ) ( r ) ( x ) ( w ) ( 1 ) ( w ) ( 1 ) ( w ) ( 1 ) 7654 3210 ? ( r ) ( x ) ponr wrst erst srst wte wt1 wt0 ponr ? wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 sclk clr clr 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 4 watchdog timer control register (wdtc) watchdog timer watch mode start timebase timer mode start sleep mode start hold status start counter clear control circuit count clock selector 2-bit counter watchdog reset generation circuit clear internal reset generation circuit clr and start-up time base counter dividing hclk by 2 hclk: oscillation clock sclk: sub clock wdcs bit of watch timer control register (wto) scm bit of clock selection register (ckscr) stop mode start mb90800 series 54 13. time-base timer the time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter (time-base counter) with synchronizing to the internal count clock (two division of original oscillation). further- more, the function of timer output of oscillation stabilization wait or function supplying operation clocks for watchdog timer are provided. (1) register list (2) block diagram timer base timer control register (tbtc) 0000a9 h ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? (r/w) ( 1 ) ? tbie tbof tbr tbc1 tbc0 reserved tbie tbof tbr resv ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer time-base timer counter dividing hclk by 2 to watchdog timer power-on reset counter clear control circuit interval timer selector tbof clear time-base timer control register (tbtc) time-base timer interrupt signal to clock controller oscillation stabilizing wait time selector tbof set ? : unused of : overflow hclk : oscillation clock *1 : the machine clock is switched from main/sub clock to pll clock. *2 : the machine clock is switched from sub clock to main clock. stop mode start hold status start ckscr : mcs = 0* 1 ckscr : scs = 0 ? 1* 2 mb90800 series 55 14. clock the clock generator controls operation of the internal clock which is the operation clock for the cpu and peripheral devices. this internal clock is referred to as machine clock and its one cycle as machine cycle. in addition, the clock generated by original oscillation is referred to as oscillation clock and that by internal pll oscillation as pll clock. (1) register list clock selection register (ckscr) 0000a1 h initial value ( r ) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 0 ) ( r/w ) ( 0 ) 15 14 13 12 11 10 9 8 mcm ( r ) ( 1 ) scm ws1 ws0 scs mcs cs1 cs0 mb90800 series 56 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 2 2 x0a x1a rst x0 x1 mclk reserved low power consumption mode control register (lpmcr) release interrupting cpu intermittent operation selector pin high - z control circuit clock selector sub clock generation circui t pin oscillation stabilization wait time selector clock selection register (ckscr) time-base timer pin peripheral clock control circuit internal reset generation circuit standby control circuit pll multiplying circuit pin pin to watchdog timer dividing by 1024 hclk : oscillation clock mclk : main clock sclk : sub clock standby control circuit cpu clock control circuit pin system clock generation circuit dividing by 2 dividing by 2 dividing by 4 dividing by 4 dividing by 4 dividing by 2 clock generation block machine clock oscillation stabilization wait pin high - z control cpu clock internal reset stop, sleep signal stop signal peripheral clock intermittent cycle selection dividing by 4 mb90800 series 57 (3) clock supply map x0 x1 x0a x1a hclk mclk sclk cpu (f 2 mc-16lx) pclk 1234 clock generation circuit oscillation circuit watch timer timer clock divider watchdog timer oscillation circuit selector time-base timer internal resources lcd controller 16-bit reload timer 8/10-bit a/d converter serial i/o free-run timer input capture pll multiplying circuit 2 division circuit 2 division circuit selector rom/ram (memory) hclk : oscillation clock frequency mclk : main clock frequency pclk : pll clock frequency sclk : sub clock frequency mb90800 series 58 15. low power consumption mode the mb90800 series have the following cpu operation modes by selecting the operation clock and operating the control of the clock. ? clock mode (pll clock mode, main clock mode and sub clock mode) ? cpu intermittent operation mode (pll clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent operation mode) ? standby mode (sleep mode, time base timer mode, stop mode and watch mode) (1) register list low power consumption mode control register (lpmcr) 0000a0 h initial value ( w ) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 slp ( w ) ( 0 ) stp spl rst tmd cg1 cg0 reserved mb90800 series 59 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 2 2 x0a x1a rst x0 x1 mclk reserved low power consumption mode control register (lpmcr) release of interrupt cpu intermittent operation selector pin high-z control circuit clock selector sub clock generation circuit pin oscillation stabilization wait time selector clock selection register (ckscr) time-base timer pin peripheral clock control internal reset generation circuit standby control circuit pll multiplying circuit pin pin to watchdog timer dividing by 1024 hclk : oscillation clock mclk : main clock sclk : sub clock standby control circuit cpu clock control circuit pin system clock generation circuit dividing by 2 dividing by 2 dividing by 4 dividing by 4 dividing by 4 dividing by 2 clock generation block machine clock release of oscillation stabilization wait pin high-z control cpu clock internal reset stop, sleep signal stop signal peripheral clock intermittent cycle selection dividing by 4 mb90800 series 60 (3) figure of status transition stp = 1 stp = 1 stp = 1 tmd = 0 tmd = 0 tmd = 0 slp = 1 slp = 1 slp = 1 mcs = 0 mcs = 1 scs = 0 scs = 0 scs = 1 scs = 1 power-on reset power supply end of oscillation stabilization wait main clock mode main sleep mode timebase timer mode main stop mode main clock oscillation stabilization wait pll clock mode pll sleep mode timebase timer mode pll stop mode main clock oscillation stabilization wait sub clock mode sub sleep mode watch mode sub stop mode sub clock oscillation stabilization wait interrupt interrupt interrupt interrupt interrupt interrupt end of oscillation stabilization wait reset external reset, watchdog timer reset, software reset, interrupt interrupt interrupt end of oscillation stabilization wait end of oscillation stabilization wait mb90800 series 61 16. timer clock output the timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the set division clock. selectable from 32/64/128/256 division of the oscillation clock. the timer clock output circuit is inactive in reset or stop mode. normally, it is active in run, sleep, or pseudo- timer mode. note : when the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output. for detail of the timebase timer?s clear condition, see the section of timebase timer in hardware manual. (1) register list (2) block diagram pll_run main_run sleep pseudo clock stop reset operation status - : unused bit initial value address : 0000af h xxxxx000 b r/w r/w r/w 15 14 13 12 11 10 9 8 ? ???? ten ts1 ts0 x0 x1 timer clock selection circuit oscillation circuit timer clock output selector time-base timer dividing by 2 mb90800 series 62 17. rom mirrorring function selection module rom mirrorring function selection module can select that ff bank where rom is located look into 00 bank among the settings of the register. (1) register list (2) block diagram note : do not access to this register in the middle of the operation of the address 008000 h to 00ffff h . - : unused bit initial value address : 00006f h xxxxxxx1 b r/w 15 14 13 12 11 10 9 8 ? ????? ? mi rom address area rom mirroring function selection f 2 mc-16lx bus ff bank 00 bank address data mb90800 series 63 18. interrupt controller interrupt control register is in the interrupt controller. the register corresponds to all i/o of interrupt function. the register has following functions; ? setting of interrupt level at correspondent peripheral circuit. (1) register list (at writing) interrupt control register address : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 0000b1 h 0000b3 h 0000b5 h 0000b7 h 0000b9 h 0000bb h 0000bd h 0000bf h icr01, 03, 05, 07, 09, 11, 13, 15 read/write ? initial value ? interrupt control register address : icr00 icr02 icr04 icr06 icr08 icr10 icr12 icr14 0000b0 h 0000b2 h 0000b4 h 0000b6 h 0000b8 h 0000ba h 0000bc h 0000be h icr00, 02, 04, 06, 08, 10, 12, 14 read/write ? initial value ? 15 14 13 12 11 10 9 8 ics2 ics3 ics1 ics0 ise il2 il1 il0 w ( 0 ) w ( 0 ) w ( 0 ) r/w ( 0 ) r/w ( 1 ) r/w ( 1 ) r/w ( 1 ) w ( 0 ) bit 7654 3210 w ( 0 ) w ( 0 ) w ( 0 ) r/w ( 0 ) r/w ( 1 ) r/w ( 1 ) r/w ( 1 ) ics2 w ( 0 ) ics3 ics1 ics0 il2 il1 il0 ise bit mb90800 series 64 (2)register list (at reading) note : do not access using the read modify write instruction because it causes a malfunction. interrupt control register address : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 0000b1 h 0000b3 h 0000b5 h 0000b7 h 0000b9 h 0000bb h 0000bd h 0000bf h icr01, 03, 05, 07, 09, 11, 13, 15 read/write ? initial value ? interrupt control register address : icr00 icr02 icr04 icr06 icr08 icr10 icr12 icr14 0000b0 h 0000b2 h 0000b4 h 0000b6 h 0000b8 h 0000ba h 0000bc h 0000be h icr00, 02, 04, 06, 08, 10, 12, 14 read/write ? initial value ? 15 14 13 12 11 10 9 8 ? ( ? ) r ( 0 ) r ( 0 ) r/w ( 0 ) r/w ( 1 ) r/w ( 1 ) r/w ( 1 ) ? ? ( ? ) ? s1 s0 ise il2 il1 il0 bit 7654 3210 ? ( ? ) r ( 0 ) r ( 0 ) r/w ( 0 ) r/w ( 1 ) r/w ( 1 ) r/w ( 1 ) ? ? ( ? ) ? s1 s0 il2 il1 il0 ise bit mb90800 series 65 (3) block diagram il2 il1 il0 32 3 3 3 judging the priority of interrupt interrupt request (peripheral resources) (cpu) interrupt level f 2 mc-16lx bus mb90800 series 66 19. lcd controller/driver the lcd controller/driver contains 24 8-bit display data memory and controls the lcd display with four common output lines and 48 segment output lines. three duty outputs can be selected to directly drive the lcd panel (liquid crystal display). ? contains an lcd driving voltage split resistor. moreover, the external division resistance can be connected. ? a maximum of four common output lines (com0 to com3) and 48 segment output lines (seg0 to seg47) are available. ? contains 24-byte display data memory (display ram). ? for the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting). ? the lcd can directly be driven. recommended mode disable (1) register list bias 1/2 duty 1/3 duty 1/4 duty 1/2 bias 1/3 bias ~ lcr (lcd control register) lcd control register (higher) (lcrh) lcd control register (lower) (lcrl) ~ lcdc range register (lcrr) 00005d h read/write initial value 00005c h read/write initial value 00005e h read/write initial value (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 vs0 (r/w) ( 0 ) ss4 cs1 cs0 ss3 ss2 ss1 ss0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 lcen (r/w) ( 0 ) css vsel bk ms1 ms0 fp1 fp0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 (r/w) ( 0 ) se4 se3 se2 se1 se0 lcr reserved reserved mb90800 series 67 (2) block diagram 4 48 v0 v1 v2 v3 com0 com1 com2 com3 seg00 seg01 seg02 seg03 seg04 ~ seg42 seg43 seg44 seg45 seg46 seg47 internal data bus lcdc range register (lcrr) main clock sub clock (32 khz) lcd control register (lcrl) prescaler timing controller display ram 24 8 bit lcd control register (lcrh) division resistor controller driver circuit of making to exchange common driver segment driver mb90800 series 68 n n n n electrical characteristics 1. absolute maximum ratings the absolute maximum ratings is based on v ss = av ss = 0.0 v. *1 : av cc should not be exceeding v cc at power-on etc. *2 : v i , v o , should not exceed vcc + 0.3 v. *3 : a peak value of an applicable one pin is specified as a maximum output current. *4 : an average current value of an applicable one pin within 100 ms is specified as an average output current. (average value is found by multiplying operating current by operating rate.) *5 : an average current value of all pins within 100 ms is specified as an average total output current. (average value is found by multiplying operating current by operating rate.) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 4.0 v av cc v ss - 0.3 v ss + 4.0 v v cc 3 av cc * 1 input voltage v i v ss - 0.3 v ss + 4.0 v *2 v ss - 0.3 v ss + 6.0 v n-ch o.d (5 v withstand voltagei/o) output voltage v o v ss - 0.3 v ss + 4.0 v *2 ?l? level maximum output current i ol11 ? 10 ma other than p74, p75, p40 to p47* 3 i ol12 ? 30 ma p74, p75, p40 to p47 (heavy-current output port) * 3 ?l? level average output current i olav1 ? 3ma other than p74, p75, p40 to p47* 4 i olav2 ? 15 ma p74, p75, p40 to p47 (heavy-current output port) * 4 ?l? level maximum total output current s i ol ? 120 ma ?l? level average total output current s i olav ? 60 ma *5 ?h? level maximum output current i oh11 ? - 10 ma other than p74, p75, p40 to p47* 3 i oh12 ? - 12 ma p40 to p47 (heavy-current output port) * 3 ?h? level average output current i ohav ? - 3ma*4 ?h? level maximum total output current s i oh ? - 120 ma ?h? level average total output current s i ohav ? - 60 ma *5 power consumption pd ? 351 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c mb90800 series 69 2. recommended operating conditions the recommended operating conditions is based on v ss = av ss = 0.0 v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.7 3.6 v at normal operating 1.8 3.6 v stop operation state maintenance ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin (resisting pressure of 5 v is v cc = 5.0 v) v ihm v cc - 0.3 v cc + 0.3 v md pin input ?l? level input voltage v il v ss - 0.3 0.3 v cc v cmos input pin v ils v ss - 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss - 0.3 v ss + 0.3 v md pin input operating temperature t a - 40 + 85 c mb90800 series 70 3. dc characteristics (v cc = av cc = 3.3 v 0.3 v, t a = - 40 to + 85 c) the dc characteristics is based on v ss = av ss = 0.0 v. (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level output voltage v oh output pins other than p40 to p47, p74, p75 i oh = - 4.0 ma v cc - 0.5 ? vcc v v oh1 p40 to p47 i oh = - 8.0 ma v cc - 0.5 ? vcc v heavy-current output port ?l? level output voltage v ol output pins other than p40 to p47, p74, p75 i ol = 4.0 ma vss ? vss + 0.4 v v ol1 p40 to p47 i ol = 15.0 ma vss ? vss + 0.6 v heavy-current output port v ol2 p74, p75 i ol = 15.0 ma ? 0.5 vss + 0.8 v open-drain pin open-drain output application voltage v d1 p74, p75 ? vss - 0.3 ? vss + 5.5 v input leak current i il all output pin v cc = 3.3 v, v ss < v i < v cc - 10 ? 10 m a pull-up resistor r up rst vcc = 3.3 v, t a = + 25 c 25 50 100 k w pull-down resistor r down md2 vcc = 3.3 v, t a = + 25 c 25 50 100 k w except flash products open drain output current i leak p74, p75 ?? 0.1 10 m a mb90800 series 71 (v cc = av cc = 3.3 v 0.3 v, t a = - 40 to + 85 c) the dc characteristics is based on v ss = av ss = 0.0 v. (continued) parameter sym- bol pin name conditions value unit remarks min typ max power supply current i cc v cc v cc = 3.3 v, internal frequency 25 mhz at normal operating ? 48 60 ma v cc = 3.3 v, internal frequency 25 mhz at flash writing ? 60 75 ma flash products v cc = 3.3 v, internal frequency 25 mhz at flash erasing ? 60 75 ma flash products i ccs v cc = 3.3 v, internal frequency 25 mhz at sleep mode ? 22.5 30 ma i ccts v cc = 3.3 v, internal frequency 3 mhz at timer mode ? 0.75 7 ma i ccl v cc = 3.3 v, internal frequency 8 khz at subclock operation, (t a = + 25 c) ? 15 140 m a mask products ? 0.5 0.9 ma flash products i ccls v cc = 3.3 v, internal frequency 8 khz at subclock sleep operation, (t a = + 25 c) ? 23 40 m a i cct v cc = 3.3 v, internal frequency 8 khz at watch mode (t a = + 25 c) ? 1.8 40 m a i cch at stop mode, (t a = + 25 c) ? 0.8 40 m a lcd division resistance r lcd v cc - v3 at lcr = 0 setting 100 200 400 k w * v cc - v3 at lcr = 1 setting 12.5 25 50 v0 - v1, v1 - v2, v2 - v3 at lcr = 0 setting 50 100 200 v0 - v1, v1 - v2, v2 - v3 at lcr = 1 setting 6.25 12.5 25 com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 3.3 v ?? 2.5 k w seg00 to seg47 output impedance r vseg seg00 to seg47 ?? 15 k w mb90800 series 72 (continued) (v cc = av cc = 3.3 v 0.3 v, t a = - 40 to + 85 c) the dc characteristics is based on v ss = av ss = 0.0 v. * : lcd internal diveded resistor can be select two type resistor by lcr (internal diveded resistor selecting bit) of lcrr (lcdc range register) . parameter sym- bol pin name conditions value unit remarks min typ max lcd leak current i lcdc v0 to v3, com0 to com3, seg00 to seg47 ?- 5 ? 5 m a mb90800 series 73 4. ac characteristics (1) clock timing (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the clock timing is based on v ss = av ss = 0.0 v. * : when selecting the pll clock, the range of clock frequency is limited. use this product within range as mentioned in ?base oscillator frequency vs. internal operating clock frequency?. parameter sym bol pin name condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 16 mhz external crystal oscillation f ch x0, x1 3 ? 25 mhz at external clock* 4.5 ? 25 multiply by 1 4 ? 12.5 multiply by 2 4 ? 8.33 multiply by 3 4 ? 6.25 multiply by 4 f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 40 ? 333 ns t lcyl x0a, x1a ? 30.5 ?m s input clock pulse width p wh p wl x0 5 ?? ns set duty ratio 50 % 3 % p wlh p wll x0a ? 15.2 ?m s set duty ratio at 30 % to 70 % as a guideline. input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 1.5 ? 25 mhz when main clock is used f cp1 ?? 8.192 ? khz when sub clock is used internal operating clock cycle time t cp ? 40 ? 666 ns when main clock is used t cp1 ?? 122.1 ?m s when sub clock is used 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl x0, x1 clock timing 0.8 v cc 0.2 v cc t cf t cr t cl p wlh p wll x0a, x1a clock timing mb90800 series 74 rating values of alternating current is defined by the measurement reference voltage values shown below : ? pll operation guarantee range relation between internal operation clock frequency and power supply voltage relation between oscillation frequency and internal operating clock frequency 3.6 3.0 2.7 1.5 4.5 16 25 pll operation guarantee range normal operation assurance range internal clock f cp (mhz) power voltage v cc (v) 25 16 12 8 6 4.5 4 3 4 4.5 6 8 12 16 25 multiply by 4 multiply by 3 multiply by 2 multiply by 1 original oscillation clock f ch (mhz) internal clock f cp (mhz) external clock 0.8 v cc 0.2 v cc 2.4 v 0.8 v input signal waveform hysteresis input pin output signal waveform output pin mb90800 series 75 (2) reset input timing (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the reset input timing is based on v ss = av ss = 0.0 v. * : oscillation time of oscillator is time until oscillation reaches 90% of amplitude. it takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a far/ceramic oscillator, and 0 milliseconds on an external clock. parameter sym- bol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main leep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ?m s at stop mode, at sub clock mode, at sub sleep mode, at watch mode rst x0 500 ns t rstl 0.2 v cc 0.2 v cc rst t rstl 0.2 v cc 0.2 v cc in normal operating, time base timer mode, main sleep mode and pll sleep mode in stop mode, sub clock mode, sub sleep mode and watch mode internal operating clock internal reset 90 % of amplitude oscillation time of oscillator wait time for stabilization oscillator execute instruction mb90800 series 76 (3) power-on reset (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the power-on reset is based on v ss = av ss = 0.0 v. notes : v cc should be set under 0.2 v before power-on rising up. these value are for power-on reset. in the device, there are internal registers which is initialized only by a power-on reset. if these initialization is executing, power-on prosedure must be obeyed by these value. parameter symbol pin name condi- tions value unit remarks min max power supply rising time t r v cc ? ? 30 ms at normal operating power supply shutdown time t off v cc 1 ? ms for repeated operation v cc v cc 2.7 0.3 v v ss t r 0.2 v 0.2 v 2.7 v t off 0.2 v sudden change of power supply voltage may activate the power-on reset function. when changing power supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown below. when raising the power, do not use pll clock. however, if voltage drop is 1mv/s or less, use of pll clock is allowed during operation. ram data hold limiting the slope of rising within 50 mv/ms is recommended. mb90800 series 77 (4) serial i/o (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the serial i/o is based on v ss = av ss = 0.0 v. notes : ac rating in clk synchronous mode. c l is a load capacitance value on pins for testing. t cp is machine cycle frequency (ns) . parameter sym bol pin name conditions value unit remarks min max serial clock cycle time t scyc sc0 to sc3 internal shift clock mode output pin : c l = 80 pf + 1ttl 8 t cp ? ns sck ? sot delay time t slov sc0 to sc3 so0 to so3 - 80 80 ns valid sin ? sck - t ivsh sc0 to sc3 si0 to si3 100 ? ns sck - ? valid sin hold time t shix 60 ? ns serial clock h pulse width t shsl sc0 to sc3 external shift clock mode output pin : c l = 80 pf + 1ttl 4 t cp ? ns serial clock l pulse width t slsh 4 t cp ? ns sck ? sot delay time t slov sc0 to sc3 so0 to so3 ? 150 ns valid sin ? sck - t ivsh sc0 to sc3 si0 to si3 60 ? ns sck - ? valid sin hold time t shix 60 ? ns internal shift clock mode external shift clock mode sc so si t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sc so si t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90800 series 78 (5) timer input timing (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the timer input timing is based on v ss = av ss = 0.0 v. (6) timer output timing (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the timer output timing is based on v ss = av ss = 0.0 v. (7) trigger input timing (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the trigger input timing is based on v ss = av ss = 0.0 v. parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tin0 to tin2 ic0 to ic1 ? 4 t cp ? ns parameter sym- bol pin name condi- tions value unit remarks min max clk - ? t out change time t to tot0 to tot2, ppg0 to ppg1, ocu0 to ocu1 ? 30 ? ns parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh t trgl int0 to int3 ? 5 t cp ? ns at normal operating 1 ?m s in stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tinx icx timer input timing clk totx ppgx ocux 2.4 v t to 2.4 v 0.8 v timer output timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl intx trigger input timing mb90800 series 79 (8) i 2 c timing (av cc = v cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the i 2 c trriger is based on av ss = v ss = 0.0 v. *1 : f cp is internal operation clock frequency. refer to ? (1) clock timing?. *2 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. parameter symbol conditions standard- mode unit min max scl clock frequency f scl when power supply voltage of external pull-up resistor is 5.0 v r = 1.0 k w , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v r = 1.0 k w , c = 50 pf* 2 0 100 khz hold time (repeated) start condition sda ? scl t hdsta 4.0 ?m s ?l? width of the scl clock t low 4.7 ?m s ?h? width of the scl clock t high 4.0 ?m s set-up time for a repeated start condition scl - ? sda t susta 4.7 ?m s data hold time scl ? sda - t hddat 0 3.45 * 3 m s data set-up time sda - ? scl - t sudat when power supply voltage of external pull-up resistor is 5.0 v f cp * 1 20 mhz, r = 1.0 k w , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v f cp * 1 20 mhz, r = 1.0 k w , c = 50 pf* 2 250 ? ns when power supply voltage of external pull-up resistor is 5.0 v f cp * 1 20 mhz, r = 1.0 k w , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v f cp * 1 20 mhz, r = 1.0 k w , c = 50 pf* 2 200 ? ns set-up time for stop condition scl - ? sda - t susto when power supply voltage of external pull-up resistor is 5.0 v r = 1.0 k w , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v r = 1.0 k w , c = 50 pf* 2 4.0 ?m s bus free time between a stop and start condition t bus 4.7 ?m s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto mb90800 series 80 5. electrical characteristics for the a/d converter (v cc = av cc = 3.3 v 0.3 v, ta = - 40 to + 85 c) the electrical characteristics for the a/d converter is based on v ss = av ss = 0.0 v. *1 : at operating, main clock 25 mhz. *2 : if a/d converter is not operating, a current when cpu is stopped is applicable (at vcc - cpu = avcc = 3.3 v) parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an11 av ss - 1.5 lsb avss + 0.5 lsb av ss + 2.5 lsb mv 1 lsb = avcc/1024 full-scale transition voltage v fst an0 to an11 avcc - 3.5 lsb avcc - 1.5 lsb avcc + 0.5 lsb mv conversion time ?? 8.64* 1 ??m s sampling time ?? 2 ??m s analog port input current i ain an0 to an11 ?? 10 m a analog input voltage v ain an0 to an11 0 ? avcc v reference voltage ? avcc 3.0 ? avcc v power supply current i a avcc ? 1.4 3.5 ma i ah avcc ?? 5* 2 m a reference voltage supplying current i r avcc ? 94 150 m a i rh avcc ?? 5* 2 m a interchannel disparity ? an0 to an11 ?? 4lsb mb90800 series 81 mb90800 series 82 6. definition of a/d converter terms resolution analog variation that is recognized by an a/d converter. the 10-bit can resolve analog voltage into 2 10 = 1024. total error this shows the difference between the actual voltage and the ideal value and means a total of error because of offset error, gain error, non-linearity error and noise. linearity error deviation between a line across zero-transition line (00 0000 0000 ? 00 0000 0001) and full-scale transition line (11 1111 1110 ? 11 1111 1111) and actual conversion characteristics. differential linear error deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. (continued) 3ff 3fe 3fd 004 003 002 001 avss (avrl) avcc (avrh) 0.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} total error digital output actual conversion characteristic v nt (measurement value) analog input total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb v ot (ideal value) = avss + 0.5 lsb [v] v fst (ideal value) = avcc - 1.5 lsb [v] 1lsb(ideal value) = avcc - avss 1024 [v] actual conversion characteristics ideal characteristics [lsb] v nt : a voltage at which digital output transitions from (n - 1) to n. mb90800 series 83 (continued) linear error in digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linear error in digital output n = v (n + 1) t - v nt } 1 lsb - 1lsb 1 lsb = v fst - v ot 1022 [v] v fst : voltage at which digital output transits from 3fe h to 3ff h . n - 1 avss (avrl) avcc (avrh) n - 2 n n + 1 actual conversion characteristic ideal characteristics v (n + 1)t (measurement value) v nt (measurement value) actual conversion characteristics linearity error differential linear error digital output digital output analog input analog input v ot : voltage at which digital output transits from 000 h to 001 h . [lsb] 3ff 3fe 3fd 004 003 002 001 avss (avrl) avcc (avrh) actual conversion characteristics {1 lsb (n - 1) + v ot } v fst v nt actual conversion characteristics ideal characteristics v ot (actual measurement value) (measurement value) (measurement value) mb90800 series 84 7. flash memory * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measuremunts into normalized value at + 85 c). parameter conditions value unit remarks min typ max sector erase time t a = + 25 c vcc = 3.0 v ? 115s excludes 00 h programming prior to erasure. chip erase time ? 9 ?m s excludes 00 h programming prior to erasure. word (16 bit width) programming time ? 16 3,600 s except for the over head time of the system. program/erase cycle ? 10,000 ?? cycle flash data retension time average t a = + 85 c 20 ?? yearss * mb90800 series 85 n n n n ordering information part number package remarks MB90F804-101pf-g MB90F804-201pf-g 100-pin plastic qfp (fpt-100p-m06) mb90803pf mb90803spf mb90800 series 86 n n n n package dimension 100-pin plastic qfp (fpt-100p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 C0.20 +.014 C.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * * mb90800 series 87 memo mb90800 series fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ preliminary 2004.07.22 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-party?s intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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